1. Field of the Invention
This invention relates to semiconductor memories and more particularly to an improved memory sense line termination circuit for coupling a memory sense line to a supply bus of relatively high pull-up voltage.
2. Description of the Prior Art
In present day semiconductor static memory systems of the type which are established as integrated circuits on the surface of a semiconductor substrate, a sense line termination circuit may comprise a single depletion mode field effect device whose drain is connected to a supply bus of high pull-up voltage Vcc and whose gate and source are connected together to the sense line. A depletion device so-connected functions as an always conductive, current limiting, variable voltage dropping impedance, coupling the sense line to the supply bus of relatively high pull-up voltage. Thus, for example, if the supply bus pull-up voltage is +5 volts, the so-connected depletion mode device will permit the sense line to be pulled down by an accessed memory cell node to close to 0 volts and will thereafter upon de-access of the memory cell, pull up the sense line to substantially the full 5 volt value of the supply bus pull-up voltage. Although a sense line having such a depletion device termination circuit has satisfactory medium power dissipation, it also has only medium switching speeds which limit the access time to the memory cells.
In another present day semiconductor static memory system, a sense line termination circuit may comprise a single enhancement mode device whose drain and gate are connected to the supply bus of high pull-up voltage Vcc and whose source is connected to the sense line. An enhancement device so-connected will in pull-up of the sense line raise the sense line to a voltage value which is one threshold voltage Vt below the high pull-up voltage and will in pull-down permit the sense line to be pulled down to the low voltage of an accessed memory node. Thus, for example, if the supply bus pull-up voltage is +5 volts and the effective threshold voltage of the enhancement field effect device is 11/2 volts, then the so-connected enhancement mode device will permit the sense line to be pulled down by an accessed memory cell node to close to 0 volts and will thereafter upon de-access of the memory cell pull up the sense line to approximately 31/2 volts which is approximately one threshold voltage below the full 5 volt value of the supply bus pull-up voltage.
In such operation the enhancement device has almost 5 volts across it following pull-down, and has approximately 11/2 volts across it following pull-up, so that it operates as a sense line load impedance having variable, very differing voltages across it during the two phases of operation of the sense line. A sense line having such an enhancement device termination circuit has somewhat higher but still only medium switching speed, and it also has undesirably high power dissipation, which limits the usability of such sense line termination circuits in large memory systems.
Thus in the prior art we have one type of sense line termination circuit (the single depletion device), whose use results in medium switching speed and medium power dissipation, and we also have in the prior art another type of sense line termination circuit (the single enhancement device as described) whose use results in somewhat higher but still medium switching speeds, but also relatively unsatisfactory high power dissipation.
The several deficiencies of these prior art sense line termination circuits have in the past been accepted as unavoidable (without introduction of clocking systems), and the selection of one or the other of the prior art termination circuits has been a standard matter of engineering compromise. It has in the past appeared logical that higher switching speeds should require higher power dissipation and that use of lower power dissipation should result in lower switching speeds, and the factors causing these limitations in operation of the prior art termination circuits have not been carefully investigated.